S. Blokzyl, M. Vodel, W. Hardt

Increasing the level of autonomy of systems demands confident controlling and task management units. To ensure a trusted system operation, several core capabilities have to be fulfilled: reliable sensing abilities, efficient data processing, and well-organised information dissemination. Dependent on the field of application, different types of sensors are required to meet the given operational tasks. In context of pattern recognition and object surveillance scenarios, electro-optical (EO) sensors offer superior sensing capabilities. Regarding to processing of high-resolution image data, real-time aspects represent one of the most challenging issues, especially in the domain of resource-limited, embedded systems. This paper presents a novel concept for hardware-accelerated computation of high-resolution EO sensor data using FPGAs (Field Programmable Gate Arrays). The concept focuses a complete integration of the image processing chain. Reconfigurable FPGA technologies combine the flexibility of general-purpose processors with the advantages of application-specific integrated circuits. We introduce two data processing approaches that utilise specific FPGA capabilities: data and task parallelisation. Data parallelisation reduces the amount of data to be treated by a discrete processing entity. Task parallelisation concatenates weak pattern detection methods to a strong detector. These strategies, used separately or combined, enable the conversion of sequential image processing chains to parallelised hardware design. The concepts in this paper improve the confidence of pattern recognition results significantly. At the same time, the computation speed increases, especially in comparison to microcontroller based processing units. This allows an energy-efficient realisation of complex high-resolution image processing tasks in resource-limited, embedded environments.

Deutscher Luft- und Raumfahrtkongress 2012, Berlin

Deutsche Gesellschaft für Luft- und Raumfahrt - Lilienthal-Oberth e.V., Bonn, 2012

Conference Paper

englisch

21,0 x 29,7 cm, 8 Seiten

urn:nbn:de:101:1-201211239114

data parallelisation, embedded image processing, hardware-acceleration, high-resolution eo sensors, parallelised hardware design, pattern recognition, real-time image processing, reconfigurable hardware, task parallelisation

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23.11.2012